// Copyright (C) 1953-2022 NUDT
// Verilog module name - testaux
// Version: V4.0.0.20221216
// Created:
//         by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
//       
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps

module testaux
(
	
	i_clk  ,
	i_rst_n,
    
    iv_addr                     ,         
    iv_wdata                    ,         
    i_wr                        ,      
    i_rd                        ,                                   
    o_wr                        ,      
    ov_addr                     ,      
    ov_rdata                    ,      
	//gmii interfaces from p0
	i_gmii_rxclk_p0,
	i_gmii_dv_p0,
	iv_gmii_rxd_p0,
	i_gmii_rx_er_p0,	
	
	i_gmii_txclk_p0,
	i_gmii_en_p0,
	iv_gmii_txd_p0,
	i_gmii_tx_er_p0,
	
	//gmii interfaces from p1
	i_gmii_rxclk_p1,
	i_gmii_dv_p1,
	iv_gmii_rxd_p1,
	i_gmii_rx_er_p1,	
	
	i_gmii_txclk_p1,
	i_gmii_en_p1,
	iv_gmii_txd_p1,
	i_gmii_tx_er_p1,
	
	//gmii interfaces from p2
	i_gmii_rxclk_p2,
	i_gmii_dv_p2,
	iv_gmii_rxd_p2,
	i_gmii_rx_er_p2,	
	
	i_gmii_txclk_p2,
	i_gmii_en_p2,
	iv_gmii_txd_p2,
	i_gmii_tx_er_p2,
	
	//gmii interfaces from p3
	i_gmii_rxclk_p3,
	i_gmii_dv_p3,
	iv_gmii_rxd_p3,
	i_gmii_rx_er_p3,	
	
	i_gmii_txclk_p3,
	i_gmii_en_p3,
	iv_gmii_txd_p3,
	i_gmii_tx_er_p3,
	
	i_cyclestart,
	iv_synclk,
	iv_hcp_mac,
	i_table_trigger0,
	i_table_trigger1,
		
	o_PTO0,
	o_PTO1,
	o_PTO2,
	o_PTO3,
	
	o_mirror_pkt_wr,
	ov_mirror_pkt	
);

input			i_clk;
input			i_rst_n;

input       [18:0]      iv_addr;                         
input       [31:0]      iv_wdata;                        
input                   i_wr;         
input                   i_rd;         
output                  o_wr              ;
output     [18:0]       ov_addr           ;
output     [31:0]       ov_rdata          ;
//gmii interfaces from p0
input			i_gmii_rxclk_p0;
input			i_gmii_dv_p0;
input	[7:0]	iv_gmii_rxd_p0;
input			i_gmii_rx_er_p0;	

input			i_gmii_txclk_p0;
input			i_gmii_en_p0;
input	[7:0]	iv_gmii_txd_p0;
input			i_gmii_tx_er_p0;
	
	//gmii interfaces from p1
input			i_gmii_rxclk_p1;
input			i_gmii_dv_p1;
input	[7:0]	iv_gmii_rxd_p1;
input			i_gmii_rx_er_p1;	
	
input			i_gmii_txclk_p1;
input			i_gmii_en_p1;
input	[7:0]	iv_gmii_txd_p1;
input			i_gmii_tx_er_p1;
	
	//gmii interfaces from p2
input			i_gmii_rxclk_p2;
input			i_gmii_dv_p2;
input	[7:0]	iv_gmii_rxd_p2;
input			i_gmii_rx_er_p2;	
	
input			i_gmii_txclk_p2;
input			i_gmii_en_p2;
input	[7:0]	iv_gmii_txd_p2;
input			i_gmii_tx_er_p2;
	//gmii interfaces from p3
input			i_gmii_rxclk_p3;
input			i_gmii_dv_p3;
input	[7:0]	iv_gmii_rxd_p3;
input			i_gmii_rx_er_p3;	
	
input			i_gmii_txclk_p3;
input			i_gmii_en_p3;
input	[7:0]	iv_gmii_txd_p3;
input			i_gmii_tx_er_p3;
	
input			i_cyclestart;
input	[63:0]	iv_synclk;
input	[47:0]	iv_hcp_mac;
input			i_table_trigger0;
input			i_table_trigger1;
	
//input	[63:0]	iv_command;
//input   		i_command_wr;        
//output  [63:0]	ov_command_ack;
//output   		o_command_ack_wr;
	
output			o_PTO0;
output			o_PTO1;
output			o_PTO2;
output			o_PTO3;

output			o_mirror_pkt_wr;
output	[8:0]	ov_mirror_pkt  ;



wire	[13:0]	rx_flowid_p0;
wire	[13:0]	rx_flowid_p1;
wire	[13:0]	rx_flowid_p2;
wire	[13:0]	rx_flowid_p3;

wire	[13:0]	tx_flowid_p0;
wire	[13:0]	tx_flowid_p1;
wire	[13:0]	tx_flowid_p2;
wire	[13:0]	tx_flowid_p3;

wire			rx_pulse_p0;
wire			rx_pulse_p1;
wire			rx_pulse_p2;
wire			rx_pulse_p3;

wire			tx_pulse_p0;
wire			tx_pulse_p1;
wire			tx_pulse_p2;
wire			tx_pulse_p3;
wire	[47:0]	wv_dmac;
wire	[1:0]	wv_mirror_mode;
wire	[6:0]	PTO_select;
wire	[127:0]	wv_pkt_abstract  ;
wire			w_pkt_abstract_wr;

wire			w_ram_rd	; 
wire	[3:0]	wv_ram_addr ;
wire	[14:0]	wv_ram_rdata;
wire	[14:0]	wv_ram_wdata;
wire			w_ram_wr    ;
wire	[63:0]	wv_command_ack_reg ; 
wire			w_command_ack_reg_wr;
wire	[63:0]	wv_command_ack_tab ; 
wire			w_command_ack_tab_wr;
wire			w_fitram_rd	   ;
wire	[3:0]	wv_fitram_raddr;
wire	[14:0]	wv_fitram_rdata;
wire			w_fifo_full;


pulse_generation pulse_generation_rx_p0(
	.i_clk			(i_clk),
	.i_rst_n		(i_rst_n),	    
	.i_gmii_clk		(i_gmii_rxclk_p0),
	.i_gmii_en		(i_gmii_dv_p0),
	.iv_gmii_data	(iv_gmii_rxd_p0),
	.i_gmii_er		(i_gmii_rx_er_p0),
	.iv_flowid		(rx_flowid_p0),
	.o_pulse   		(rx_pulse_p0)
);

pulse_generation pulse_generation_rx_p1(
	.i_clk			(i_clk),
	.i_rst_n		(i_rst_n),
	
	.i_gmii_clk		(i_gmii_rxclk_p1),
	.i_gmii_en		(i_gmii_dv_p1),
	.iv_gmii_data	(iv_gmii_rxd_p1),
	.i_gmii_er		(i_gmii_rx_er_p1),
	.iv_flowid		(rx_flowid_p1),
	.o_pulse   		(rx_pulse_p1)
);

pulse_generation pulse_generation_rx_p2(
	.i_clk			(i_clk),
	.i_rst_n		(i_rst_n),
	
	.i_gmii_clk		(i_gmii_rxclk_p2),
	.i_gmii_en		(i_gmii_dv_p2),
	.iv_gmii_data	(iv_gmii_rxd_p2),
	.i_gmii_er		(i_gmii_rx_er_p2),
	.iv_flowid		(rx_flowid_p2),
	.o_pulse   		(rx_pulse_p2)
);

pulse_generation pulse_generation_rx_p3(
	.i_clk			(i_clk),
	.i_rst_n		(i_rst_n),
	
	.i_gmii_clk		(i_gmii_rxclk_p3),
	.i_gmii_en		(i_gmii_dv_p3),
	.iv_gmii_data	(iv_gmii_rxd_p3),
	.i_gmii_er		(i_gmii_rx_er_p3),
	.iv_flowid		(rx_flowid_p3),
	.o_pulse   		(rx_pulse_p3)
);

pulse_generation pulse_generation_tx_p0(
	.i_clk			(i_clk),
	.i_rst_n		(i_rst_n),
	
	.i_gmii_clk		(i_gmii_txclk_p0),
	.i_gmii_en		(i_gmii_en_p0),
	.iv_gmii_data	(iv_gmii_txd_p0),
	.i_gmii_er		(i_gmii_tx_er_p0),
	.iv_flowid		(tx_flowid_p0),
	.o_pulse   		(tx_pulse_p0)
);

pulse_generation pulse_generation_tx_p1(
	.i_clk			(i_clk),
	.i_rst_n		(i_rst_n),
	
	.i_gmii_clk		(i_gmii_txclk_p1),
	.i_gmii_en		(i_gmii_en_p1),
	.iv_gmii_data	(iv_gmii_txd_p1),
	.i_gmii_er		(i_gmii_tx_er_p1),
	.iv_flowid		(tx_flowid_p1),
	.o_pulse   		(tx_pulse_p1)
);

pulse_generation pulse_generation_tx_p2(
	.i_clk			(i_clk),
	.i_rst_n		(i_rst_n),
	
	.i_gmii_clk		(i_gmii_txclk_p2),
	.i_gmii_en		(i_gmii_en_p2),
	.iv_gmii_data	(iv_gmii_txd_p2),
	.i_gmii_er		(i_gmii_tx_er_p2),
	.iv_flowid		(tx_flowid_p2),
	.o_pulse   		(tx_pulse_p2)
);

pulse_generation pulse_generation_tx_p3(
	.i_clk			(i_clk),
	.i_rst_n		(i_rst_n),
	
	.i_gmii_clk		(i_gmii_txclk_p3),
	.i_gmii_en		(i_gmii_en_p3),
	.iv_gmii_data	(iv_gmii_txd_p3),
	.i_gmii_er		(i_gmii_tx_er_p3),
	.iv_flowid		(tx_flowid_p3),
	.o_pulse   		(tx_pulse_p3)
);
pulse_select pulse_selectn_inst(
	.i_clk				(i_clk),
	.i_rst_n			(i_rst_n),
	.i_rx_pulse0		(rx_pulse_p0),
	.i_rx_pulse1		(rx_pulse_p1),
	.i_rx_pulse2		(rx_pulse_p2),
	.i_rx_pulse3		(rx_pulse_p3),
	.i_tx_pulse0		(tx_pulse_p0),
	.i_tx_pulse1		(tx_pulse_p1),
	.i_tx_pulse2		(tx_pulse_p2),
	.i_tx_pulse3		(tx_pulse_p3),
	.iv_pto_select		(PTO_select),
	.i_table_trigger0	(i_table_trigger0),
	.i_table_trigger1	(i_table_trigger1),
	.i_cyclestart		(i_cyclestart),
	.o_PTO0				(o_PTO0),
	.o_PTO1				(o_PTO1),
	.o_PTO2				(o_PTO2),
	.o_PTO3				(o_PTO3)
);

configuration_parse_and_encapsulate_taux_reg configuration_parse_and_encapsulate_taux_reg_inst(
	.i_clk					(i_clk),
	.i_rst_n				(i_rst_n),
	
	.iv_command       		(64'b0),//(iv_command),
    .i_command_wr     		(1'b0 ),//(i_command_wr),        
    .ov_command_ack   		(wv_command_ack_reg  ),
    .o_command_ack_wr 		(w_command_ack_reg_wr),
	
	.ov_flowid_reg_rx0		(rx_flowid_p0),
	.ov_flowid_reg_rx1		(rx_flowid_p1),
	.ov_flowid_reg_rx2		(rx_flowid_p2),
	.ov_flowid_reg_rx3		(rx_flowid_p3),
		  
	.ov_flowid_reg_tx0		(tx_flowid_p0),
	.ov_flowid_reg_tx1		(tx_flowid_p1),
	.ov_flowid_reg_tx2		(tx_flowid_p2),
	.ov_flowid_reg_tx3		(tx_flowid_p3),
	
	.ov_PTO_select_reg		(PTO_select),
	.ov_dmac		        (wv_dmac       ),
	.ov_mirror_mode		    (wv_mirror_mode)
);
configuration_parse_and_encapsulate_taux_table configuration_parse_and_encapsulate_taux_table_inst(
	.i_clk					(i_clk),
	.i_rst_n				(i_rst_n),
	
	.iv_command       		(64'b0),//(iv_command),
    .i_command_wr     		(1'b0 ),//(i_command_wr),        
    .ov_command_ack   		(wv_command_ack_tab  ),
    .o_command_ack_wr 		(w_command_ack_tab_wr),
    
	.ov_ram_addr 	        (wv_ram_addr),	 
	.ov_ram_wdata           (wv_ram_wdata), 
	.o_ram_wr               (w_ram_wr),
	.iv_ram_rdata           (wv_ram_rdata),
	.o_ram_rd    	        (w_ram_rd)	
);

suhddpsram16x15_rq suhddpsram16x15_rq_inst(
.rsta                         (!i_rst_n),
.rstb                         (!i_rst_n),
.regcea                       (1'b1),
.regceb                       (1'b1),
     
.addra                        (wv_ram_addr),
.addrb                        (wv_fitram_raddr),
.clka                         (i_clk),
.clkb                         (i_clk),     
.dina                         (wv_ram_wdata),
.dinb                         (15'h0),                             
.ena                          (1'b1),
.enb                          (1'b1),                            
.wea                          (w_ram_wr),
.web                          (1'b0),                        
.douta                        (wv_ram_rdata),
.doutb                        (wv_fitram_rdata)
);
                     
mux_taux mux_taux_inst(
	.i_clk					(i_clk),
	.i_rst_n				(i_rst_n),
	
	.iv_command_ack_reg     (wv_command_ack_reg  ),
    .i_command_ack_reg_wr   (w_command_ack_reg_wr), 
                             
	.iv_command_ack_tab     (wv_command_ack_tab  ),
    .i_command_ack_tab_wr   (w_command_ack_tab_wr), 
	
    .ov_command_ack   		(),//(ov_command_ack),
    .o_command_ack_wr 		() //(o_command_ack_wr)
);


packet_aggreation packet_aggreation_inst(
.i_clk			(i_clk),
.i_rst_n		(i_rst_n),

.i_gmii_rxclk_p0(i_gmii_rxclk_p0),
.i_gmii_dv_p0   (i_gmii_dv_p0   ),
.iv_gmii_rxd_p0 (iv_gmii_rxd_p0 ),
.i_gmii_rx_er_p0(i_gmii_rx_er_p0),	
.i_gmii_txclk_p0(i_gmii_txclk_p0),
.i_gmii_en_p0   (i_gmii_en_p0   ),
.iv_gmii_txd_p0 (iv_gmii_txd_p0 ),
.i_gmii_tx_er_p0(i_gmii_tx_er_p0),
                 
.i_gmii_rxclk_p1(i_gmii_rxclk_p1),
.i_gmii_dv_p1   (i_gmii_dv_p1   ),
.iv_gmii_rxd_p1 (iv_gmii_rxd_p1 ),
.i_gmii_rx_er_p1(i_gmii_rx_er_p1),	
.i_gmii_txclk_p1(i_gmii_txclk_p1),
.i_gmii_en_p1   (i_gmii_en_p1   ),
.iv_gmii_txd_p1	(iv_gmii_txd_p1	),
.i_gmii_tx_er_p1(i_gmii_tx_er_p1),
	             	
.i_gmii_rxclk_p2(i_gmii_rxclk_p2),
.i_gmii_dv_p2	(i_gmii_dv_p2	),
.iv_gmii_rxd_p2	(iv_gmii_rxd_p2	),
.i_gmii_rx_er_p2(i_gmii_rx_er_p2),	
.i_gmii_txclk_p2(i_gmii_txclk_p2),
.i_gmii_en_p2	(i_gmii_en_p2	),
.iv_gmii_txd_p2	(iv_gmii_txd_p2	),
.i_gmii_tx_er_p2(i_gmii_tx_er_p2),
                 
.i_gmii_rxclk_p3(i_gmii_rxclk_p3),
.i_gmii_dv_p3	(i_gmii_dv_p3	),
.iv_gmii_rxd_p3	(iv_gmii_rxd_p3	),
.i_gmii_rx_er_p3(i_gmii_rx_er_p3),	
.i_gmii_txclk_p3(i_gmii_txclk_p3),
.i_gmii_en_p3	(i_gmii_en_p3	),
.iv_gmii_txd_p3	(iv_gmii_txd_p3	),
.i_gmii_tx_er_p3(i_gmii_tx_er_p3),
		
.iv_mirror_mode	(wv_mirror_mode),
.iv_syn_clk		(iv_synclk   ),
.i_fifo_full	(w_fifo_full ),
.o_fitram_rd	(w_fitram_rd	 ),
.ov_fitram_raddr(wv_fitram_raddr ),
.iv_fitram_rdata(wv_fitram_rdata ), 
		  
.ov_pkt_abstract  (wv_pkt_abstract  ),
.o_pkt_abstract_wr(w_pkt_abstract_wr)
);

packet_mirror packet_mirror_inst(
.i_clk					(i_clk),
.i_rst_n				(i_rst_n),

.o_fifo_full		    (w_fifo_full),

.iv_pkt_abstract       	(wv_pkt_abstract  ),
.i_pkt_abstract_wr     	(w_pkt_abstract_wr),        

.iv_dmac				(wv_dmac),
.iv_smac		        (iv_hcp_mac),
	  
.ov_mirror_pkt			(ov_mirror_pkt),
.o_mirror_pkt_wr		(o_mirror_pkt_wr)
);                                         

endmodule 